This application is related to the transmission and reception of a channel in a downlink signal in wireless communication systems including the Frame Control Header (FCH) defined in the wireless LAN/MAN standards specified under the IEEE 802.16 for wireless communications using orthogonal frequency division multiplexing (OFDM) and orthogonal frequency division multiple access (OFDMA).
OFDM and OFDMA wireless communication systems under IEEE 802.16 use a network of base stations to communicate with wireless devices or mobile stations registered for services in the systems based on the orthogonality of frequencies of multiple subcarriers (currently 1028 subcarriers) and can be implemented to achieve a number of technical advantages for wideband wireless communications, such as resistance to multipath fading and interference. Each base station emits radio signal that carry data such as voice data and other data content to wireless devices. Such a signal from a base station includes an overhead load, in addition to the data load (voice and other data), for various communication management functions. Each wireless device processes the information in the overhead load of each received signal prior to processing the data.
Under the current versions of the IEEE 802.16 standard for the OFDMA systems, every downlink subframe from a base station includes a preamble and a FCH following the preamble as part of the overhead load. The preamble includes information for searching a cell and a cell sector within a cell and for synchronizing a mobile station in both time and frequency with the observed downlink signal. The FCH part of the downlink subframe includes 24 bits with information on the downlink transmission format (i.e., the DL-MAP) and control information for the downlink data reception (i.e., allocation of the 1028 subcarriers in the current downlink frame). Due to the nature of the information in the FCH, if the reception of FCH fails, the following downlink operations on the receiver side cannot be properly executed. Accordingly, the robustness of proper reception of the FCH is important to the overall system throughput.
FIGS. 1A and 1B illustrate the FCH channel encoding in a base station and the FCH channel decoding in a mobile station, respectively, under versions of IEEE 802.16 as of today. In the FCH encoding shown in FIG. 1A, the 24 bits of information in the FCH are repeated once by a sequence repeater 102 to produce a sequence of 48 bits, i.e., concatenating the 24-bit sequence and its identical duplicate sequence in time. The 48-bit output sequence is then randomized with a randomizing sequence by a modulo-2 adder 104. The addition of the 48-bit sequence and the randomizing sequence on a bit-by-bit basis produces a 48-bit randomized sequence. Next, a rate ½ (R=½) tail-biting convolutional coding is performed on each bit by encoder 106 to produce two encoded bits so that the 48-bit randomized sequence is encoded as a 96-bit output FCH sequence for transmission by the base station. This convolutional coding adds redundancy to the output sequence against bit errors that may occur during the signal transmission and forms the forward error correction (FEC) mechanism for controlling the bit errors in broadcasting downlink signals.
FIG. 1B shows the Viterbi decoding operation at a receiving mobile station under the versions of IEEE 802.16.
First, the received 96 symbols in the FCH sequence are converted into 96 “soft” symbols by applying a soft metrics to the received encoded bits. Each received encoded bit is not represented by a “hard” one or zero but by a multi-level “soft” value that represents the maximum likelihood that the encoded bit is to be either one or zero. The Viterbi decoding algorithm is known to have better performance with soft input symbols. A Viterbi tail-biting decoder 122 is then used to decode the 96 soft symbols into 48 “hard” bits of zeros and ones. Hence, in this context, the Viterbi decoder 122 is a soft-input-hard-output device or operator. The output bit sequence from the Viterbi decoder 122 is further de-randomized with the same randomizing sequence as used at the transmitter side by a modulo-2 adder 124. Referring to FIG. 1A, this decoding process in FIG. 1B is a reverse process of the encoding. Hence, after the de-randomization, the resulting sequence has 48 bits of “0” or “1” bits and, if no decoding error occurs, should be two identical 24-bit parts like the 48-bit sequence prior to the randomization step in the encoding process. A bit selector 126 then determines the final 24-bit FCH reception by choosing either 24-bit part in the 48-bit sequence.